1. Field of the Invention
The present invention relates to a solid-state imaging device and an image capture apparatus. More particularly, the invention is directed to a solid-state imaging device and an image capture apparatus which, by setting a predetermined number, two or more, of rows or a predetermined number, two or more, of columns to a single group, sequentially read signal charges for each group.
2. Description of Related Art
In X-Y addressable solid-state imaging devices typically represented by CMOS (Complementary Metal Oxide Semiconductor) image sensors, pixels can be selected in units of rows, columns, or pixels, from a pixel array section in which pixels including photoelectric conversion elements are arranged two-dimensionally in a matrix form, so that by specifying an arbitrary area in the pixel array section, pixel information in the arbitrary area can be partially cut out and read. See Japanese Patent Application Publication No. JP 2001-45383 (Patent Document 1), for example.
FIG. 5 is a schematic diagram for explaining a related-art CMOS image sensor, and FIG. 6 is a schematic diagram for explaining an example of a pixel circuit configuration for a certain pixel thereof. The CMOS image sensor herein shown includes a pixel array section 102 having pixels 101 including photoelectric conversion elements arranged two-dimensionally in a matrix form, a vertical scanning circuit 103, a column circuit (signal processing circuit) 104, a horizontal scanning circuit 105, a horizontal signal line 106, an output circuit 107, a timing generator (TG) 108 and so on. The pixel array section also has vertical signal lines 109, one being provided for each vertical pixel column.
Each pixel 101 forms a pixel circuit which has, in addition to the photoelectric conversion element, e.g., a photodiode 110, four transistors, e.g., a transfer transistor 111, a reset transistor 112, an amplifying transistor 113, and a selecting transistor 114. As these transistors, e.g., n-channel MOS transistors are used.
The transfer transistor 111 transfers a signal charge (an electron, here) which is photoelectrically converted by the photodiode 110 and stored at the transfer transistor 111, to a floating diffusion (FD) section 115 when a gate transfer pulse TRG is applied thereto. The reset transistor 112, connected between the FD section 115 and a power supply line for a power supply voltage VDD, resets a potential of the FD section 115 when a reset pulse RST is applied to its gate prior to the transfer of the signal charge from the photodiode 110.
The amplifying transistor 113 outputs a potential of the FD section 115 after the reset by the reset transistor 112 as a reset level, and also a potential of the FD section 115 after the transfer by the transfer transistor 111 as a signal level. The selecting transistor 114 selects the pixel 101 when a selection pulse SEL is applied to its gate, and outputs the reset level and the signal level supplied sequentially from the amplifying transistor 113, to a corresponding vertical signal line 109.
Here, a shutter operation of sweeping out unnecessary charges stored in the photodiodes of pixels before the storing of signal charges is started is performed by applying a transfer pulse TRG to the gate of the transfer transistor 111 and a reset pulse RST to the gate of the reset transistor 112 simultaneously.
Electronic shutter systems for image sensors include, mainly, a global shutter system and a rolling shutter system. The global shutter system performs a shutter operation on all pixels simultaneously, whereas, as shown in FIGS. 7A and 7B, the rolling shutter system temporally shifts areas for performing shutter operations from one area to another. It is noted that FIG. 7B shows shutter operation timings with a horizontal axis indicating a time [H] (1H: one horizontal transfer period) and a vertical axis indicating a row address, and that FIG. 7A represents a state at a time n[H] as a physical image. In addition, CMOS type image sensors mainly employ the rolling shutter system.
FIG. 11 of the above-mentioned Patent Document 1 shows the related-art CMOS image sensor capable of partially cutting out and reading pixel information in an arbitrary area in the pixel array section.